A Comprehensive Approach to Assessing and Analyzing 1149.1 Test Logic

IEEE 1149.1-1990 Standard Test Access Port and Boundary Scan Application Note

For sys tem or board d iagnost ics , AT6000 Series devices can be programmed with the 1149.1 standard test logic and then reprogrammed for normal operation when the diagnostics are comple te . The area and per fo rmance overhead of the test logic does not impact normal operation in the device because it is replaced by the logic for normal function. All mandatory test instructions can be execute...

Backplane Test Bus Applications For IEEE STD 1149.1

Prior to the mid 1980s, the dominance of through-hole packaging of integrated circuits (ICs) provided easy access to nearly every pin of every chip on a printed circuit board. Providing accessibility and controllability for board testing was simply a matter of probing the board. With the advent of surface mount packaging, the accessibility for probing printed circuit boards began to diminish. L...

AN-890 P1149.1A Extensions to IEEE-STD-1149.1-1990

Since publication of IEEE-1149.1-1990/ANSI 1, 2, 3, extensions and requests for clarifications have been adopted by the IEEE 1149.1 Working Group. The original standard established a common, industry-wide methodology for the application of scan test access. The rapid acceptance of this standard and use by semiconductor designers, test engineers and systems developers has resulted in questions n...

An IEEE 1149.1 Based Logic/Signature Analyzer in a Chip

BIST for network on chip communication infrastructure based on combination of extended IEEE 1149.1 and IEEE 1500 standards

In this paper we propose a BIST based method to test network on chip (NOC) communication infrastructure. The proposed method utilizes an IEEE 1149.1 architecture based on BIST to at-speed test of crosstalk faults for inter-switch links as well as an IEEE 1500-compliant wrapper to test switches themselves in NOC communication infrastructure. The former architecture includes enhanced cells intend...